The subject matter disclosed herein relates to integrated circuit devices. More particularly, the subject matter relates to processes in forming integrated circuit devices.
As integrated circuit (IC) technologies have advanced, the size of these devices has correspondingly decreased. Smaller ICs call for greater control over device topography. For example, when patterning upper electrodes in an IC capacitor device, conventional approaches may fail to adequately control the etching process, and cause dielectric damage proximate the capacitor. In order to control this unreliable process, conventional methods employ additional masking processes, which can be time consuming and expensive.